This invention relates to circuit design, and more particularly to the low-noise generation and synchronization of multiple phases of a reference clock.
A variety of devices, including, for example, circuit-level devices, integrated-circuit-level devices, board-level devices, and system-level devices, often need various phases of a reference clock. Known techniques for providing these phases include global generation and distribution, synchronization of locally generated phases using, for example, phase locked loops (xe2x80x9cPLLsxe2x80x9d) or delay locked loops (xe2x80x9cDLLsxe2x80x9d), and feedback-free architectures.